This invention relates to a device, and particularly to a semiconductor device having a hierarchical bit line structure.
A semiconductor device in which bit lines are hierarchized has been proposed in order to ensure compatibility between high integration and high speed. Such a semiconductor device is disclosed in Japanese Laid-Open Patent Publication No. 2004-158519 (Patent Document 1).
Furthermore, there is known a semiconductor memory device in which a local bit line is connected to a global bit lines at both ends thereof via NMOS (n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor) transistors. Such a semiconductor device is disclosed in Japanese Laid-Open Patent Publication No. 2006-32577 (Patent Document 2).
Still furthermore, there is known a semiconductor device in which bit line selection switches are provided at both ends of a hierarchical local bit line to increase rewriting current for a resistance change type memory by connecting the local bit line with a global bit line. Such a semiconductor device is disclosed in Japanese Laid-Open Patent Publication No. 2009-271985 (Patent Document 3).